Job Description:

- Physical design from RTL or Netlist to GDSII

- Typical tasks include Logic Rule Checker, Design for Testability, Floorplan, Clock tree generation, Place and Route, Crosstalk analysis and IR Drop check, Static Timing Analysis and test vector generation.

- Primarily focus on 90nm and 65nm process technologies and design methodologies.

- Report to Engineering Manager.

Requirements:

- Candidate must have a Bachelor’s Degree or above in electronic engineering or related field.

- Candidate must have logic design and CMOS technology background.

- Dedicated and hard working with good interpersonal and communication skills.

- English writing and speaking are required and Japanese speaking is a plus.

- Self motivated to learn new technology and methodology.

职责描述:

- 从RTL或网表到GDSII的物理设计;

- 主要工作包括逻辑规则检测、DFT、Floorplan、时钟树生成、布局布线、Crosstalk 分析、电压降分析、静态时序分析STA、测试模式生成;

- 主要针对90纳米和65纳米加工技术和设计方法;

- 汇报给工程技术经理.

职位要求:

- 具备微电子或工程类相关专业的学士或以上学位;

- 有逻辑设计和CMOS技术经验;

- 工作努力、勤奋，很好的团队协作、沟通能力;

- 良好的英语书写和交流能力，能用日语交流的更佳;

- 具备对新的知识及技术的良好学习能力.