Job Responsibilities:
Independently specify, design, implement, verify and document hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- Ph.D., M.S. with at least 3 years of experience, or B.S. with 5 years of experience in related areas
- Have at least 2 years of experience in processor, memory controller, PCI, or networking equipment design
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools.
- Have a track record of successful completion of complex design projects for at least 2 years
- Good programming skills in C.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Familiarity with Synopsys Design Compiler, ModelSim, Prime Time.
- Skillful in C, C++, shell scripts, Python, and/or Perl.
