Job Responsibilities:
With help from senior staff, specify, design, implement, verify and document hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- M.S. or B.S. with at least 2 years of relevant experience.
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools.
- Have a track record of successful completion of complex design projects for at least 1 year
- Good programming skills in C.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Familiarity with Synopsys Design Compiler, ModelSim, PrimeTime.
- Skillful in C, C++, shell scripts, Python, and/or Perl.
