u        Responsibility:

  As a Design Engineer, you will be a key member of the architecture group. You will model the architecture with RTL, verify the consistency of RTL against software model, propose and extract layout and timing model for architecture development, evaluate layout feasibility and timing for new architecture

u        Requirements:

²        MSEE/CS or above

²        Have at least 2 years experience in ASIC logic design and verification, synthesis and STA

²        Have clear understanding of CMOS transistor level and gate level circuit and timing

²        Ability to work in a team and to closely interact with other groups

²        Good scripting skills with Perl or Python

²        Good at English writing and speaking

u        Preferences:

²        Experience with FPGA application

²        Knowledge of DFT architecture

²        knowledge of on-chip bus protocols (AHB, Avalon, Wishbone)