Responsibilities:
Design and develop telecom/networking ASIC
Involved in architecture exploration and discussion
Write detailed design document
Write RTL code
Unit simulation and module-level synthesis
Cooperate with verification team to verify chip
Cooperate STA and back-end team to do back-end processes
Skills required:
4+ years experience in design complex ASIC/FPGAs.
Good knowledge of Networking, Ethernet, Telecom
Outstanding written and verbal communication skills
Capability of critical thinking, challenging design intent
Demonstrated understanding of networking/telecom concepts.
Education:
Requires MSEE/CS combined with 4+ yrs related experience or BSEE/CS with 6+ yrs relevant experience