About Brite Semiconductor Company:- Brite Semiconductor is a fabless ASIC company delivering the most cost-effective, predictable and reliable custom ASIC solution to electronics product customers worldwide.Brite-Semi’s OpenMODEL™ is the semiconductor industry's first end-to-end custom ASIC solution based on a revolutionary business model that provides a seamless, low-cost, low risk alternative to traditional models for complex ASIC design and development.

We offer a C&B Package with basic salary plus allowance plus medical and life insuranc and stock option opportunity.

Position Description:
As a senior member of the team you will be responsible for ensuring customer success through various design serve participation.  A qualified applicant for this position would be responsible for the development and support of customer based design from concept to netlist generation and verification, and with a responsibility for driving the design quality to success. 

Qualifications:
• Solid knowledge and experience in logic design, familiar with Verilog / VHDL coding, coding style verification ie. nLint
• Hands on experience with ASIC EDA tools used in synthesis (DC), static timing analysis (STA ie. Prime time), DCT / RC physical, and pre layout / post layout formal verification, SDC generation/analysis and timing budgeting, clock and layout constraints generation,
• Hands on experiences in block level / IP logic design / integration of RTL and netlist at chip level
• Experience in tests and test benches development
• Good written and verbal communication in Mandarins and English; Excellent interpersonal and team work skills
• Design service experience is a plus
• Experience with C / Tcl scripting / system Verilog is a plus

 

l        熟悉逻辑设计,熟悉Verilog和VHDL语言，以及verification code style（nLint）

l        熟练掌握ASIC EDA综合工具,STA，Pre-layout，GLS，Check clock timing 和 timing constraint

l        熟悉IP Block，SOC，NetList

l        熟悉Bench测试和环境

l        熟练口语英文和普通话；良好团队合作精神

l        有IC Design服务的经验为佳