Description:
-Responsible for validating Implementation tools and design flows for accuracy, performance and usability, which encompass Astro, IC Compiler, JupiterXT, Physical Compiler, Low Power Flow and so on.
-Work independently defining testing strategy & flow, creating testing plans, project planning etc.
Requirements:
-BS in CS/EE with 5+ years of relevant experience or MS with 3+ years
-Familiar with EDA industry or IC design especially in back-end flow.
-Experience in place & route, static timing analysis, delay calculation etc. is a plus.
-Experience in software testing is a plus
-Knowledge in verilog/VHDL is a plus
-Knowledge in perl/shell/tcl programming is a plus
-Good written and verbal English communication skills are necessary.