Company Introduction: Availink Inc. is a technology-driven fabless semiconductor company, focusing on the multimedia and digital TV industries. Availink Inc. is backed by premiere financial institutions, with offices in China and the United States and with targeted consumer markets around the world. By grouping a great team of professionals, building multiple product lines in fast growing markets, and attracting first-tier customers, Availink is positioned to grow into a significant player in the field. If you are a hands-on, results-oriented and energetic individual, and like to take this opportunity to grow and strive to achieve the best results, Availink will offer you a challenging and rewarding career.

Location: Beijing , China

Job Description: In this role you will participate in design and implementing structural and gate-level RTL for highly complex digital communication and multimedia ASIC's . Responsibilities include micro-architecture definition, logic design, DFT and timing closure; other responsibilities may include block level verification, and FPGA prototyping .

Candidate Qualifications:

• BS or MS degree in Electrical Engineering or Computer Science
• 3-5 years experience in micro-architecture and RTL logic design (Verilog and/or VHDL).
• Good knowledge in Synthesis, Static Timing Analysis, Debug
• Basic lab skills. Working knowledge of FPGA based prototyping.
• Strong software skills (C/C++ programming, low level hardware interface programming) is desired
• Strong UNIX scripting skills required, Perl/TCL/bash/csh
• Excellent communication and presentation skills
• Well organized, methodical, and detail oriented;
• Team player, and easy to work with