工作经验：三年以上
学历：本科
职位描述：
完成高级模拟混合信号以及闪存芯片的集成电路掩膜设计；进行芯片布局规划以优化芯片尺寸和电路功能；进行电路规划和构造，包括关键信号，电源走线以及模拟布局方针等；进行布局的DRC和LVS验证。
要求：
本科及以上学历；至少3年使用Cadence Virtuoso XL，Calibre DRC进行芯片设计的经验；熟练芯片设计布局，能够熟练使用CAD工具，例如： DREC，LVS，并且使用其进行编程；有较强的解决问题的能力；具有团队精神。

Responsibilities:
1.Perform challenging IC mask design of advanced analog mixed signal and flash memory IC's
2.Develop layout floor plans to optimize die size and circuit performance
3.Plan and construct circuits, including critical signals and power bussing to analog layout guidelines
4.Perform DRC and LVS verification of layout

Requirements:
1.Bachelor degree or higher preferred
2.Minimum of 4 experience in IC layout.Use of Cadence Virtuoso XL,Calibre DRC
3.Thorough understanding of IC layout design including use of CAD tools such as DREC,LVS and skill programs
4.Must be good at problems solving
5.Must have the ability to communicate effectively with different levels of people

Remuneration will be commensurate with experience and qualification. Interested parties please send your detailed resume indicating job reference number with current and expected salary to recruit.hk@atmel.com.

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