Responsibility:

1 Responsible for IC digital designs for Mixed Signal Products.
2 Logic design & implementation by Verilog on module level and for SOC integration.
3 Testbench generation, module/chip/system level verifications using Verilog or other verification languages.
4 Module level synthesis, DFT and timing analysis.
5 FPGA prototyping definition and implementation for complex IPs and SOC design.
6 IP creation by Matlab, C high-level modeling and RTL coding by Verilog.
7 SOC platform definition, IP integration and implementation for SOC design.

Requirements:

1 Master or above in Electronic, Communications or Microelectronics Engineering.
2 At least 2+ years of experience in digital design based on high-level languages(preferable Verilog and/or C),with knowledge of IC design flow, including coding, simulation, verification, synthesis and DFT.
3 Familiar with mainstream EDA tools from Synopsis, Cadence and Mentor, like NC-Verilog, VCS, DC/PC, PrimeTime, Fastscan and so on.
4 Familiar with DSP theory and fundamental implementations.
5 Additional hands-on experience on IP creation and SOC definition, integration and verification is a big plus.
6 Good written and oral English communication skills.
7 Familiarity with laboratory equipment is a plus.
8 Good team work spirit, easy to cooperate with team members.