Required experience:

- Bachelor of Science in Electronics Engineering qualification

- 5+ years ASIC design experience as ASIC FAE, customer engineer and / or design center engineer

- Prefer hands on Verilog gate-level simulation experience

- Prefer maintain good relationship with LENOVO

- Prefer working knowledge of at least three of the following: DRAM/Flash embedded ASICS, Synthesis, DFT/ATPG, Static Timing Analysis, ARM Core Embedded ASICs, or Mixed Signal Embedded ASICs, etc.

Responsibilities:

- Assist ASIC customers in use of our ASIC design kits and methodology including libraries, digital / analog IP's, DFT, test integration, delay calculation, layout interface, test pattern generation, and/or bonding diagram generation. 

-  Interface between customer and layout engineer during layout stage.  Interface between customer and our US headquarter to answer questions related to IP, tools, design flow, test pattern debug, etc. 

-  Serve as primary technical contact for customer through all stages of ASIC lifecycle, from design win to prototype delivery.

- Ensure smooth, on-time implementation of ASIC projects by tracking schedule and following up technical issues / action items.

Interested Parties, please send your ENGLISH resume to:

info@carnegie-consultancy.com