Job Description:
Functional verification of complex networking/Telecom ASIC/FPGAs.
Develop verification environment using HVL, such as Vera/Specman
Develop random, pseudo-random and directed tests
Establish verification effectiveness using assertion/functional/code coverage and code reviews
RTL and gates simulation, debug and root cause
Regression and debug

Skills required:
2+ years experience in design verification on complex ASIC/FPGAs.
1+ projects verification experience
knowledge of Networking, Ethernet, Telecom
Knowledge of HVL(such as Vera, Specman) verification platforms
Good coding skills (such as E, Vera, C++, Verilog, Perl, TCL)
Good written and verbal communication skills in both mandarin and English

Education and experience:
Requires MSEE/CS combined with 1-2+ yrs related experience or BSEE/CS  with 2+ yrs relevant experience