JOB RESPONSIBILITIES

l         Responsible for working with Chip architect to define DFT plan for platform SOC chips.

l         Interface with front-end logic design team to implement DFT structures during the logic design phase. This includes providing guidelines for clock, and reset control, as well as others that would affect testability and coverage.

l         Will be responsible for Internal-Scan, MBIST, JTAG, as well as mixed-signal test and hard-IP DFT signoff.

l         Will also be responsible for ATPG and sanity test-vector simulations for Internal scan, both pre and post-layout with timing.

l         Interface with back-end physical design team to implement scan-reordering and timing closure for test related logic.

l         Interface with manufacturing test-house to debug production test-vectors for final test and wafer-tests.

GENERAL SKILLS REQUIRED:

l         Should be familiar with SOC design flow in general.

l         Knowledge of synopsys DFT compiler ( design compiler) and Tetramax a must.

l         Knowledge of primetime a plus.

l         Familiar with MBIST.

l         Knowledge of test-pattern conversion tools like VTRAN a plus.

l         Familiarity of packaged test-vectors from 3^rd party hard-IP vendors a plus.

l         Must have deep knowledge of muxed internal scan methodology and options to debug any test related issues.

l         Knowledge of verilog and HDL simulation needed.

l         Must have taped-out at least one 0.18u or preferable 0.13u design at the DFT signoff level.