Responsibilities
*Lead a small group to act as main interface between company project team and design service vendor to facilitate physical implementation
*Corporate with logic design team to cover library setup, synthesis, formal verification, DFT insertion and test vector generation, chip IO timing/SSO SPICE simulation, PD constraints generation/validation, FloorPlanning and STA
*Corporate with design service vendor to achieve active project GDSII signoff in shortest time
*Build up team capability gradually during the course of working with design service vendor and setup in house PD flow/methodology

Requirements
*Bachelors Degree in Electrical Engineering with 3+ years experience
*Good level of understanding regarding ASIC PD flow
*Hands-on experiences on synthesis, formal verification, DFT insertion and test vector generation, chip IO timing/SSO SPICE simualtion, PD constraints generation/validation,FloorPlanning and STA
Track record of participating GDSII TO
*Good communication and presentation skill
Experiences on  placement, clock tree synthesis, routing, RC extraction, power planning and analysis, layout verification is a plus
Experiences on Magma and Synopsys EDA tool chain is a plus

Candidate will be involved in layout design of complex networking systems/boards.  Must have a strong PCB layout implementation skills.  The role will require close interaction with board design engineers.

Location: Hangzhou