Job Responsibilities:

Independently design, verify re-usable HDL modules optimized for structured ASIC or FPGA device architectures.

Requirements:

• B.S. with at least 2 years' working experience, or M.S. with 1 years' project experience in logic design.
  
• Good knowledge on Verilog/VHDL.
  
• Familiar with logic synthesis, simulation and verification tools, such as DC, Modelsim/VCS.
  
• Good programming skills in script language, such as TCL, perl.
  
• Good documentation and communication skill, in both Chinese and English

Preferences:

• Familiar with Static Timing Analysis using PrimeTime.
  
• Skillful in shell scripts, Python, and/or Perl.

职位职责：

独立地对 ASIC 或 FPGA 的优化硬件可重用 HDL 模型进行描述，设计，执行，并验证

职位要求：

• 大学本科以上学历，有 2 年工作经验；或者硕士学历，有 1 年逻辑设计项目经验
  
• 熟悉 Verilog/VHDL ，熟练使用逻辑综合，仿真和验证工具，如 DC, Modelsim/VCS

符合以下条件者优先考虑：

.较好的脚本语言编程能力，如 TCL, perl.

.能够熟练使用 PrimeTime 做静态时序分析，精通 Shell 脚本， Python ， Perl