Job Responsibilities:
Independently specify, design, implement, verify hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
Requirements:
- M.S. with at least 2 years of experience, or B.S. with 4 years' experience in processor, memory controller, PCI, or networking equipment design;
- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools;
- Familiar with Front-end Flow, logic synthesis using Synopsys' Design Compiler, timing check with PrimeTime, test bench development and verification and design-for-test scan insertion;
- Have a track record of successful achievement in complex design projects;
- Good programming skills in script language, such as tcl, perl.
- Good documentation and communication skill, in both Chinese and English.
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Skillful in C, C++, shell scripts, Python, and/or Perl.
职位职责:
独立地对 ASIC 或 FPGA 的优化硬件可重用 HDL 模型进行描述,设计,执行,并验证
职位要求:
- 硕士学历 2 年以上工作经验;或者本科学历,有 4 年以上在处理器,内存控制其, PCI ,或网络相关芯片设计等方面工作经验
- Verilog , VHDL 设计经验丰富,熟练使用逻辑综合,仿真和验证工具
- 熟悉前端设计流程,熟练使用 Synopsys' Design Compiler, PrimeTime
- 有很强的脚本语言编程能力,如 TCL, perl
- 优秀的中英文交流及文档书写能力
- 熟悉 FPGA 者优先
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