Job Responsibilities:
Independently specify, design complex SoC verification platform to verify complex SoC.
Requirements:
- M.S. in E.E. with more than 3 years' complex SoC verification experience;
- Hands on HDL RTL coding, and assertion-based verification methods;
- Familiar with and related EDA verification tools (such as VCS +Vera, Questasim) ;
- Familiar with C, system-verilog language;
- Good documentation and communication skill,in both Chinese and English.
Preferences:
- Familiar with script languages such as csh, tcl or perl
- Familiar with FPGA
职位职责:
独立地设计复杂的片上系统验证平台
职位要求:
- E.E .硕士学历, 3 年以上复杂片上系统验证经验
- 熟悉 RTL 级 HDL 编码及验证方法
- 熟练使用相关 EDA 验证工具,如 VCS +Vera, Questasim 等
- 熟悉 C, System-Verilog 语言
- 优秀的中英文交流及文档书写能力
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