Job description:

       Design, generate and verify specific Characterization Vehicle® test chip layouts to characterize clients’ manufacturing processes and quantify impact of design on product performance and yield. Focus on short flow (BEOL, FEOL) test chips.

       Use PDF proprietary automated layout tools including layout generators, routers and packers to create, place and route CV test chip structures.

       Generate all collateral needed for testing, inspection, analysis, and documentation of CV® Test Chips.

       Participate with client in detailed review of test chip including post-OPC data review and pre mask-making reviews

       Work closely with PDF CV Analysis Methods to create an optimal design of experiments for CV® test chips.

Required skills and experience:

       Sound understanding of semiconductor manufacturing process and transistors

       Experience with semiconductor layout methods and layout tool suites (e.g., Cadence, Mentor, etc).

       Working knowledge of DRC and LVS tools and deck creation and applicatoin

       Basic knowledge of Unix scripting languages (e.g., perl, CSH, SH, Tcl, etc)

       Basic knowledge of parametric test methods

       Self-motivated and highly professional including some experience with customer interactions

       Familiarity with interpreting and using Design Rule Manuals for deep sub-micron semiconductor processes (both foundry and IDM)

Job desirables:

       Experience with Cadence Virtuoso and/or Cadence SKILL programming language

       Experience with Mentor Graphics Calibre DRC

       Experience with any part of Design for Manufacturability including design modification, verification, algorithms or failure analysis

       Experience using circuit modeling software (HSPICE, Spectre, etc)

       Familiarity with semiconductor reticle-making practices (mask data prep, dummy fill algorithms, basics of OPC, mask fracturing and biasing, etc)